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			    <title>阿憨-激情燃烧岁月</title>
			    <link>http://blog.dicder.com/?uid-3</link>
			    <description>阿憨(ahan)  Verification Specialist 
Email:ahan.mail@gmail.com</description>
			    <copyright>Copyright(C) 阿憨-激情燃烧岁月</copyright>
			    <generator>SupeSite/X-Space</generator>
			    <lastBuildDate>Fri, 09 Jan 2009 12:11:38 GMT</lastBuildDate><item>
								<title>How to redirection the message during batch mode in Modelsim?</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-288</link>
								<description><![CDATA[<P>Here is an example of a batch mode simulation using redirection of std input and output:<BR>vsim counter &lt; yourfile &gt; outfile<BR>where "yourfile" is a script containing various ModelSim command;</P>
<P>-quiet only shut off the loading message...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Thu, 16 Aug 2007 13:23:36 GMT</pubDate>
							</item>
							<item>
								<title>Why we should do gate-level simulation?</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-287</link>
								<description><![CDATA[<P>SNUG:All My X’s Come From Texas…Not!!<BR>Matt Weber<BR>Jason Pecor<BR>Silicon Logic Engineering</P>
<P>In a recent ESNUG article (<A href="http://www.deepchip.com/items/0421-01.html">http://www.deepchip.com/items/0421-01.html</A>), eighteen engin...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Wed, 15 Aug 2007 11:10:45 GMT</pubDate>
							</item>
							<item>
								<title>英雄帖－招募合作者！</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-259</link>
								<description><![CDATA[<P>本人想出一本关于systemverilog/Questa/验证方法学的书。</P>
<P>现想招募合作者若干人：</P>
<P>1。熟悉systemverilog/SVA</P>
<P>2。熟悉Questa</P>
<P>3。了解验证方法学</P>
<P>满足上述条件其中一个即可，欢迎在校从事IC设计验证的研究生加入。</P>
<P>在职...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Tue, 22 May 2007 11:16:26 GMT</pubDate>
							</item>
							<item>
								<title>Mentor Graphics-Advanced Verification Methodology Cookbook</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-237</link>
								<description><![CDATA[<H1><FONT size=4>Advanced Verification Methodology Cookbook</FONT></H1><!--/pageElement:PAGETITLE--><!--pageElement:MAINCONTENT--><A name=top></A>
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<TABLE id=idLayout3854 cellSpacing=0 cellPadding=0 width="100%" summary="...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Fri, 16 Mar 2007 10:03:30 GMT</pubDate>
							</item>
							<item>
								<title>Mentor Graphics-Questa Verification Platform</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-235</link>
								<description><![CDATA[<H1><FONT size=4>Questa AFV (Advanced Functional Verification)</FONT></H1><!--/pageElement:PAGETITLE--><!--pageElement:MAINCONTENT--><A name=top></A>
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<TABLE id=idLayout3854 cellSpacing=0 cellPadding=0 width="100%" summar...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Fri, 16 Mar 2007 09:51:45 GMT</pubDate>
							</item>
							<item>
								<title>SYNOPSYS-----Discovery Verification Platform</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-58</link>
								<description><![CDATA[Discovery Verification Platform <BR>Delivering a new level of verification excellence for complex chip design <BR><BR><BR><BR><BR>Overview<BR>The Discovery&#8482; Verification Platform is an integrated system, RTL, equivalence checking, and mixed-signa...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Wed, 08 Mar 2006 21:09:03 GMT</pubDate>
							</item>
							<item>
								<title>SYNOPSYS－－Galaxy Design Platform</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-57</link>
								<description><![CDATA[Galaxy Design Platform <BR>The Most Comprehensive Solution for Advanced Integrated Circuit Design <BR><BR><BR><BR><BR>Overview<BR>The Galaxy&#8482; Design Platform is an open, integrated design implementation platform with best-in-class tools, enabling...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Wed, 08 Mar 2006 21:00:48 GMT</pubDate>
							</item>
							<item>
								<title>阿憨新作－－－Debussy使用指南</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-53</link>
								<description><![CDATA[<P>最近公司项目验证，经常使用debussy，原来看过debussy的useguide，但是觉得他们写得太繁琐，所以想重新浏览一遍，并把关键点和使用技巧记录下来供大家参考：）<BR>先特奉上，请各位兄弟朋友多多提意见！<BR><BR>感谢回复的那些兄弟，本来想等全部写完了再放上来，既然大...]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Fri, 17 Feb 2006 22:47:42 GMT</pubDate>
							</item>
							<item>
								<title>阿憨的发表的论文－－－AMBA总线协议及其在SOC的应用</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-52</link>
								<description><![CDATA[一年前曾对AMBA总线协议做了学习，写了一篇论文，也算是自己在SOC方面的一点认识吧。<BR>还请其他做SOC的兄弟多多指导，多提出批评，感谢老扁师兄在提供了不少好资料：） ]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Wed, 18 Jan 2006 22:23:00 GMT</pubDate>
							</item>
							<item>
								<title>阿憨的发表的论文－－－3G终端Viterbi译码器的硬件实现</title>
								<link>http://blog.dicder.com/?uid-3-action-viewspace-itemid-51</link>
								<description><![CDATA[把论文传上来，第一可以供入门的人参考，第二希望有更多的人讨论viterbi译码器的实现。 ]]></description>
								<category>blog</category>
								<author>ahan</author>
								<pubDate>Wed, 18 Jan 2006 22:07:30 GMT</pubDate>
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