The only way to ensure the integrity of the largely manual transition from the system-level to RTL is to put together an environment that can effectively verify the design at multiple levels of abstraction.  It must also make it easy for users to take advantage of functional coverage, constrained-random stimulus generation, assertions, and other advanced verification techniques.

The Mentor Graphics® Advanced Verification Methodology is the first, true, system-level-to-RTL verification methodology that allows you to apply leading-edge verification technologies to designs at multiple levels of abstraction, using multiple languages. The AVM provides libraries of base classes and modules in open-source form and uses TLM interfaces as the communication mechanism between verification components.

The AVM kit includes extensive runnable examples, in both SystemVerilog and SystemC, and extensive, book-form documentation that discusses the different concepts introduced in each example.

• Multiple Levels of Abstraction.True system-level-to-RTL verification methodology
• Advanced Verification. Supports advanced verification technologies, such as constrained-random
  6M7d5pS4R1B0stimulus, functional coverage, and assertions.
• Testbench Reuse.Includes a set of executable examples, libraries, and extensive documentation
  
  SP Y7S8V[$u` H0(the Verification Cookbook) for developing modular, reusable testbenches.

Open Source.Open and non-proprietary code is freely available to anyone under an open-sourceDICDER -- 博客专栏 O_;C8gPw^;aX Apache license. Standard Languages.Based on standard languages, it uses only 100 percent LRM-compliant codeDICDER -- 博客专栏6aCi$K NJ SystemVerilog and SystemC. As a result, code is reusable and “future-proof.” TLM Standard.Based on the OSCI TLM standard, implemented in both SystemC and 2B_kY)tOc)v;J0SystemVerilog, making it easy to link to embedded software and transaction-level models.