Why we should do gate-level simulation?

SNUG:All My X’s Come From Texas…Not!!DICDER -- 博客专栏!p#dC9q4]#?t'j1g8o
Matt WeberDICDER -- 博客专栏n`}[h'Iq/KS:h
Jason PecorDICDER -- 博客专栏X|{\#J;KS2a-a
Silicon Logic Engineering

In a recent ESNUG article (http://www.deepchip.com/items/0421-01.html), eighteen engineers
;@9ZZ8\#NPUj0shared their view of the current usefulness of gate level simulation. Only one of those engineersDICDER -- 博客专栏*r(? q
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has completely removed gate level simulation from their design flow. The other engineers listedDICDER -- 博客专栏 TdBs$d
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many reasons for continuing to do some level of gate level simulation.
%e&\?-Z2zR"iX7xN01. Since scan and other test structures are added during and after synthesis, they are notDICDER -- 博客专栏4A2Og]Yy&d6F
checked by the rtl simulations and therefore need to be verified by gate level simulation.
WJ)l,gD%yWdfs$A02. Static timing analysis tools do not check asynchronous interfaces, so gate level simulationDICDER -- 博客专栏"GF+`/qmd
is required to look at the timing of these interfaces.
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xxP;|C?c03. Careless wildcards in the static timing constraints set false path or mutlicycle path
%hv]:f SE8} |Q0constraints where they don’t belong.DICDER -- 博客专栏1I/^U,g5l5D
4. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths
e W5s6K1@O0or multicycle paths in the static timing constraints.DICDER -- 博客专栏 Z;M2@ OC$KD
5. Using create_clock instead of create_generated_clock leads to incorrect static timingDICDER -- 博客专栏,?#OCuD~
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between clock domains.
R8o:a&[0g06. Gate level simulation can be used to collect switching factor data for power estimation.
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a07. X’s in RTL simulation can be optimistic or pessimistic. The best way to verify that theDICDER -- 博客专栏}#`_dD
design does not have any unintended dependence on initial conditions is to run gate level

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+FuSb:yJ6r$p08. It’s a nice “warm fuzzy” that the design has been implemented correctly.