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			    <title>alphame的个人空间</title>
			    <link>http://blog.dicder.com/?uid-4</link>
			    <description></description>
			    <copyright>Copyright(C) alphame的个人空间</copyright>
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			    <lastBuildDate>Sat, 22 Nov 2008 05:58:57 GMT</lastBuildDate><item>
								<title>SystemVerilog实现Fat12文件系统</title>
								<link>http://blog.dicder.com/?uid-4-action-viewspace-itemid-4730</link>
								<description><![CDATA[<P>&nbsp;最近用systemverilog实了一个简单的fat12文件系统，做为一实验，目的不是实现一个完善的系统，所以只实现了一些基本的东西。下面是系统的框架和一些说明。</P>
<P>限制：任何一级目录不能大于一个扇区，<BR>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; Fat不能大于一个扇区...]]></description>
								<category>blog</category>
								<author>alphame</author>
								<pubDate>Tue, 22 Apr 2008 22:48:12 GMT</pubDate>
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								<title>usb中的crc算法证明</title>
								<link>http://blog.dicder.com/?uid-4-action-viewspace-itemid-4496</link>
								<description><![CDATA[<P>&nbsp;&nbsp;&nbsp; crc广泛应用于通信中的数据校验，usb也不例外。usb中的crc算法规定如下：<BR>&nbsp;&nbsp;&nbsp;“ For CRC generation and checking, the shift registers in the generator and checker are seeded with an all-<BR>ones pattern.&nbsp; For each...]]></description>
								<category>blog</category>
								<author>alphame</author>
								<pubDate>Sat, 29 Mar 2008 10:24:35 GMT</pubDate>
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