Why we should do gate-level simulation?

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Matt Weber
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hw;TJ q,P9732Jason Pecor
n3?)eStI,l9732Silicon Logic Engineering

In a recent ESNUG article (http://www.deepchip.com/items/0421-01.html), eighteen engineers
5AwkUIzA-s9732shared their view of the current usefulness of gate level simulation. Only one of those engineersDICDER -- 博客专栏4g"tp4B;]
has completely removed gate level simulation from their design flow. The other engineers listedDICDER -- 博客专栏*DYO"T ?yOc
many reasons for continuing to do some level of gate level simulation.
0e|1XZHy.LH.lW]3Ix ]97321. Since scan and other test structures are added during and after synthesis, they are notDICDER -- 博客专栏#i9RW0o6k#I;~
checked by the rtl simulations and therefore need to be verified by gate level simulation.DICDER -- 博客专栏V sl&@;s z6z
2. Static timing analysis tools do not check asynchronous interfaces, so gate level simulation
Mz%``9b7px"y#qSq9732is required to look at the timing of these interfaces.
3am9Quu/K_Me(^$n#`97323. Careless wildcards in the static timing constraints set false path or mutlicycle path
'Q.L*ttV{ t$_ x9732constraints where they don’t belong.DICDER -- 博客专栏:W-f
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4. Design changes, typos, or misunderstanding of the design can lead to incorrect false paths
.U$P+q$g*G9732or multicycle paths in the static timing constraints.
Onp] ?6b97325. Using create_clock instead of create_generated_clock leads to incorrect static timing
7|%N3_j/aPP HMg6|v1U9732between clock domains.
3V/S l5[$i+_97326. Gate level simulation can be used to collect switching factor data for power estimation.
W[%X{5Ye!k?97327. X’s in RTL simulation can be optimistic or pessimistic. The best way to verify that the
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S2G9MV-?9732design does not have any unintended dependence on initial conditions is to run gate levelDICDER -- 博客专栏,JD.uMI+@
simulation.
ir3HZ4L3v/[97328. It’s a nice “warm fuzzy” that the design has been implemented correctly.