急问关于spectreverilog的仿真问题

我用spectreverilog仿一个混合信号电路,模拟部分是schematic,数字部分是verilog代码

电路已经搭好了,config也做了,IE也设好了,自己感觉设的没有问题,但是一仿真就这样:

*USRERR:  Net net040<3>, in module VCO_all, lib hsc_863, view schematic
        requires the generation of Hierarchical Interface Element (IE) inside      
       a cellview having the view name that is a member of the analog
       or digital stop view set. Such an IE will be ignored by the simulator.
       Please change your design to avoid this limitation.

我在partitioning options里面设的是:
Analog stop view list: spectre schematic
digital stop view list:  symbol verilog functional

请求高手指点,是哪里出了问题?

万分感激!!!!!!!!!!!!!!!!!!!!!!!